Heterogeneous Multicore Architecture - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 15

digital signal processing. The FE has an internal 30-KB LM but does not have a
DTU. The on-chip DMA controller (DMAC) that can be used in common by on-chip
units or a DTU of another core is used to transfer data between the LM and other
memories. The MX has 1,024-way single instruction multiple data (SIMD) architec-
ture that is suitable for highly data-intensive processing such as video recognition.
The MX has an internal 128-KB LM but does not have its DTU, just as with the FE.
In the chip photograph in Fig. 2.5 , the upper-left island includes four CPUs, and the
lower-left island has the VPU with other blocks. The left cluster in Fig. 2.6 includes
these left islands and a DDR3 port depicted at the lower-left side. The lower-right
island in the photo in Fig. 2.5 includes another four CPUs, the center-right island has
four FEs, and the upper-right has two MXs. The right cluster in Fig. 2.6 includes
these right islands and a DDR3 port depicted at the upper-right side. With these 15
on-chip heterogeneous cores, the chip can execute a wide variety of multimedia and
digital-convergence applications at high-speed and low-power consumption. The
details of the chip and its applications are described in Chaps. 4 - 6 .

2.2 Address Space

There are two types of address spaces defined for a heterogeneous multicore chip.
One is a public address space where all major memory resources on and off the
chip are mapped and can be accessed by processor cores and DMA controllers in
common. The other is a private address space where the addresses looked for from
inside the processor core are defined. The thread of a program on a processor core
runs on the private address space of the processor core. The private address space of
each processor core is defined independently.
Figure 2.7a shows a public address space of the heterogeneous multicore chip
depicted in Fig. 2.1 . The CSM, the LMs of CPU #0 to CPU #m, the LMs of SPP a #0
to SPP a #n, and the LMs of SPP b #0 to SPP b #k are mapped in the public address
space, as well as the off-chip main memory. Each DTU in each processor core can
access the off-chip main memory, the CSM, and the LMs in the public address
space and can transfer data between various kinds of memories. A private address
space is independently defined per processor core. The private addresses are gener-
ated by the PU of each processor core. For a CPU core, the address would be
generated during the execution of a load or store instruction in the PU. Figure 2.7b, c
shows examples of private address spaces of a CPU and SPP. The PU of the CPU
core accesses data of the off-chip main memory, the CSM, and its own LM mapped
on the private address space of Fig. 2.7b . If the LM of another processor core is not
mapped on this private address space, the load/store instructions executed by the PU
of the CPU core cannot access data on the other processor core's LM. Instead, the
DTU of the CPU core transfers data from the other processor core's LM to its own
LM, the CSM, or the off-chip main memory using the public address space, and the
PU accesses the data in its private address space. In the SPP example (Fig. 2.7c ),
the PU of the SPP core can access only its own LM in this case. The data transfer