Hardware Reference
In-Depth Information
Fig. 2.7 Public/private
address spaces
a
b
Off-chip
main memory
Off-chip
main memory
CSM
CSM
LM (CPU #0)
LM
LM (CPU #m)
LM (SPP a #0)
Private address space
(CPU core)
c
LM (SPP b #k)
LM
Other resources
Private address space
(SPP core)
Public address space
Fig. 2.8 Private address
space (Hierarchical Harvard)
PU
LM i
LM d
LM i
LM d
LM 2
LM 2
Hierarchical-Harvard structure
Private address space
between its own LM and memories outside the core is done by its own DTU on the
public address space.
The address mapping of a private address space varies according to the structure
of the local memory. Figure 2.8 illustrates the case of the hierarchical Harvard
structure of Fig. 2.2c . The LM i and LM d are first-level local memories for instruc-
tions and data, respectively. The LM 2 is a second-level local memory that stores
both instructions and data. The LM i , LM d , and LM 2 are mapped on different
address areas in the private address space. The PU accesses each LM with different
addresses.
The size of the address spaces depends on the implementation of the heteroge-
neous multicore chip and its system. For example, a 40-bit address is assigned for a
public address space, a 32-bit address for a CPU core's private address space, a
16-bit address for the SPP's private address space, and so on. In this case, the sizes
of each space are 1 TB, 4 GB, and 64 KB, respectively. Concrete examples of this
are described in Chaps. 3 and 4 .
 
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