Heterogeneous Multicore Architecture - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 14

Fig. 2.5 Heterogeneous
multicore chip

CPU #7

CPU #3

CPU #2

CPU #2

CPU #6

CPU #2

LCPG LCPG

CPU #1
CPU #0

CPU #1

LCPG CPU #5

CPU #4

CPU #1

CPU #0 CPU #0

LCPG

LCPG

LCPG

Local Clock
Pulse Generator

LCPG LCPG

LM LM

LM:16/16KB
DSM:64KB
DTU

LM:16/16KB
DSM:64KB
DTU

I/OLRAM:16/16KB
URAM:64KB

I/OLRAM:16/16KB
URAM:64KB

DMA controller

CSM #1
256KB

CSM #0
256KB

DMAC
#1

DTU

DTU

On-chip bus #0 On-chip bus #1

FE #0 MX #0 DDR3

port #1

DDR3
port#0

VPU DMAC

#0

LM:30KB
FE #1
FE #2
FE #3

LM:30KB
MX #1

LM:300KB
DTU

Matrix Processor

Video Processor Unit Off-chip

DDR3 DRAM

Off-chip
DDR3 DRAM

Flexible Engine

Fig. 2.6 Block diagram of heterogeneous multicore chip

Three types of SPPs are embedded on the chip. The first SPP is a video processing
unit (VPU, see Sect. 3.4) which is specialized for video processing such as MPEG-4
and H.264 codec. The VPU has a 300-KB LM and a DTU built-in. The second and
third SPPs are four flexible engines (FEs, see Sect. 3.2), and two matrix processors
(MXs, see Sect. 3.3), and they are included in another cluster. The FE is a dynami-
cally reconfigurable processor which is suitable for data-parallel processing such as