Software Environments - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 171

Op Address SrcID

ACL: Access Control List

Address Mask[31:xx] SrcID Mask[7:0] Pwr

Address [31:xx]
Address Mask[31:xx]

SrcID[7:0]

SrcID Mask[7:0] Pwr

Address [31:xx] SrcID[7:0] Prd

Address [31:xx] SrcID[7:0] Prd

“ Write ”

“Read”

Fig. 5.12 Access control of physical partitioning controller

We assigned an SrcID to each initiator module and used a control register address
as an identifier for the DEST field. The size of the address range should be a power
of 2, and its start address should be a multiple of the alignment, which must be a
power of 2 and a multiple of the size of the address range.

5.2.5.2 Implementation of PPC

Figure 5.12 shows the PPC structure. The SRC field consists of an SrcID and an
SrcID mask; the DEST field consists of an address and address mask; and the AUTH
field consists of two bits—one for read permission and one for write permission.
The PPC checks every access request by comparing a set consisting of an operation,
target address, and SrcID with all ACL entries using the logical circuit shown in the
figure. When the PPC finds a match for an ACL entry, it authorizes the access
request, and the PPC passes the access request to the target module. When the PPC
finds no match for an ACL entry, it does not authorize the access request; rather, the
PPC blocks it and generates a deny signal to start error handling.
The PPC modules are located between the internal system bus and the bus-target
modules—that is, the DBSC, SHPB and HPB bus bridges, PCIe, and DMAC (see
Fig. 5.13 ). The PPC has six subblocks—DBSC-PPC, LBSC-PPC, SHPB-PPC,
HPB-PPC, DMAC-PPC, and PCI-PPC—each of which has its own set of registers