Hardware Reference
In-Depth Information
Targets
Initiators
PPC
RAM
DBSC
Control registers
DMAC
CPU #0
CPU #1
Area #0
HPB
DMAC 0-5
DMAC 6-11
Area #1
TMU-05
TMU6-11
CPU #2
CPG
Access Check List
CPU #3
Area #C
CPU #2
Mem A#0 RW
WDT
GPIO
CPU #3
Mem A#0 RW
SDIF0
SDIF1
CPU #0
Mem A#1 RW
DMAC 0-5
DMAC 6-11
CPU #2
DMAC 0-5
RW
CPU #0 DMAC 6-11
DMAC 0-5
DMAC 6-11
RW
RW
RW
RW
Mem A#0
Mem A#1
PCIe 0
DU
HSPI
SSI0-1
SSI2-3
CPU #2
Ether
Ether
Mem A#0 RW
RW
PCIe 1
PCIe 2
PCIe 0
PCIe 1
CPU #2
DU
DU
Mem A#0
R
RW
SCIF0-1
CPU #2
PCIe 0
PCIe 0
Mem A#0 RW
I2C0
I2C1
CPU #2
RW
SCIF 0-1
SCIF2-5
PCIe 2
CPU #0
SCIF 2-5
RW
CPU #2
TMU 0-5
RW
SHPB
USBF
RW
CPU #0
TMU 6-11
ROM
LBSC
HAC0
CPU #0
GPIO
RW
DU
INTC
USBH
Area #0
HAC1
Ether
USBF
INTC2
LCPG 0
LCPG 1
Area #1
USBH
Fig. 5.11
Physical partitioning controller (PPC)
5.2.5.1
Access Control of Physical Partitioning Controller
The PPC is located between the access initiator modules and the access target mod-
ules. It checks every access request and blocks requests that are not authentic. The
PPC contains an access checklist (ACL) to set access authorization rules, and the
ACL defines the processor's partition configuration. The ACL consists of several
register entries, each having three fields:
An SRC fi eld, which speci fi es an access initiator
A DEST field, which specifies an access target
An AUTH field, which specifies authorized operation for both the SRC and DEST
fi elds
The processor has multiple-channel devices, such as a DMAC, PCIe, TMU,
SCIF, audio codec I/F (HAC), serial sound I/F (SSI), and I2C. The PPC segments
them into groups of channels and recognizes each group as a separate module so
that each domain uses one group's function exclusively. The PPC also segments
RAM and ROM into several memory areas so that a domain can use them as private
memory. Moreover, several domains can access a shared RAM area to communicate
with each other. Therefore, the PPC recognizes each initiator and target, indicated
in Fig.
5.11
, as separate modules.
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