VGA (640 x 480), 15fps
MX- 2 (30.6GOPS)
Total 4.4 GB
System con fi guration and memory usage of prototype digital TV
Chip Integration and Evaluation
The RP-X was fabricated using a 45-nm low-power CMOS process. A chip micro-
graph of the RP-X is in Fig. 4.28 . It achieved a total of 13,738 MIPS at 648 MHz by
the eight SH-X4 cores measured using the Dhrystone 2.1 benchmark, and consumed
3.07 W at 1.15 V including leakage power.
The RP-X is a prototype chip for consumer electronics or scientific applications.
As an example, we produced a digital TV prototype system with IP networks (IP-
TV) including image recognition and database search. Its system configuration and
memory usage are shown in Fig. 4.29 . The system is capable of decoding 1,080i
audio/video data using a VPU and an SPU on the OS#1. For image recognition, the
MX-2s are used for image detection and feature quantity calculation, and the