Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 89

MPC
Inst. Pointer_0 Pointer_1

PE

Entry #n PE

PE

Operand_A :
00000110

Operand_B :
00000101

Temp. Reg.

Cycle

2bit
ALU

Read xx

k 00 00 01 10 00 00 01 01

+

Read

01
11

Read

k+1 00 00 01

00 00 01 10 10

+

Write

Read

01
10

k+2 00 00 01 10 01 00 00 11

+

Write

Fig. 3.62 Operation fl ow of H-ch

communications among PEs. The powerful processing performance of MX can be
realized with the cooperation between H-ch and V-ch. The design concept of MX is
based on the SIMD architecture. Therefore, all PEs and SRAM data registers oper-
ate in the same way. The operations of the processing array portion are controlled
by SIMD control signals generated by the MPC. The MPC generates the control
signals by decoding the instructions stored in its instruction RAM. That is, all the
operations of MX-1 can be controlled by the sequence programs loaded in the
instruction RAM as in the case of conventional DSPs.
The operation flow diagram of the addition operation utilizing H-ch is explained
in Fig. 3.62 . One column of data register array and one PE are grouped as one entry
which is an operation unit of H-ch. In each PE, 2-bit-ALU and temporary registers
which temporarily store the readout data from the data registers are equipped. As
the PE is 2-bit grained, the operands stored in the data registers are processed in a
bit-serial way. At the cycle k, 2 bits (LSB) of Operand_A are read out, and they are
stored in the temporary registers at the next cycle k + 1. At this k + 1 cycle, 2 bits of
Operand_B are read out from the other plane of data register array and added with
the stored data in the temporary registers.
The output data of PE are written back to the data registers within the same cycle
of k + 1, utilizing the read-modify-write operation of SRAM. We have adopted this
two-operand type operation, such as B = A + B; therefore, each SRAM memory cell
behaves as if it is an accumulator. In addition, with the double-sided memory structure
shown in Fig. 3.62 , the processing throughputs are enhanced up to two-bit-grained