Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 90

a

Read-out

Sense
Amp.

RS
Latch

Execution
(Modify)

SRAM
(1 Column)

PE

Write
Driver

Write-back

Operation Flow

b

CLK

Word-Line
(SRAM)

Operation

RMW RMW RMW

Read Exec. Write

Timing Diagram

Fig. 3.63 Read-modify-write based data-path design (© 2007 IEEE)

addition per 1 cycle. With these techniques, if 2,048 sets of 16-bit-additions are
executed with 2,048 entries in parallel, MX-1 can process all the data in ten cycles
(including the overhead of pipelined operation); therefore, a set of operands stored in
1 entry can be processed in approximately 0.005 cycle (ten cycles/2,048 entries). Note
that the practical implementation of PE and double-sided memory is completely sym-
metrical, temporary registers, and PEs have connections with both sides of the data
register array (required selectors not described in Fig. 3.62 ). The design concept of
H-ch proposed here significantly contributes to the enhancement of the processing
throughput while maintaining the area efficiency.
Figure 3.63 shows the proposed design technique employed in this work, which
is based on the read-modify-write (RMW) operation of SRAM. The main feature
of this design is that the required sequential operations of the H-ch processing, readout,
execution, and write-back, can be completed in one clock cycle. The asynchronous
RS-latch located next to the sense amplifier is implemented for holding the readout
data until the write-back operation is completed. As shown in the timing diagram of
Fig. 3.63b , the word line of SRAM can be activated at every clock cycle, and that
brings a high data processing throughput. In addition, by adopting the proposed
design methodology, the size of PE can be reduced as small as possible by eliminat-
ing unnecessary pipeline registers. Although the proposed scheme reduces the max-
imum operating frequency, portable multimedia devices do not require high-frequency
system clock, and reducing the required clock cycles for data processing is more
important to build up a high-performance engine.