Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 110

Figure 5.9 Pipelining of an FIR filter

Now we use one delay to form the real multiplier:

x k ¼ D N 1 ð a 1 D x k 1 þ Du k Þ

ð 5 : 26 Þ

^

¼ D N 1 ð a 1 ^

x k 1 þ Du k Þ : ð 5 : 27 Þ

We use one more D to form the real adder

x k ¼ D N 2 ð a 1 D x k 1

þ u k Þ : ð 5 : 28 Þ

Finally, we put D ¼ z 1 and x k 1 ¼ z 1 x k to obtain

x k ¼ z N þ 2 ð a 1 ^

z 1 x k þ z 1 u k Þ

ð 5 :

29 Þ ^

¼ z N þ 1 ð a 1 ^

x k

þ u k Þ : ð 5 : 30 Þ

For x k ¼ x k , N must be zero. However, N 1 is required for a causal filter.

Solutions to this problem exist. They use a higher-order difference equation
representation of the filter with equivalent characteristics, so feedback loop delay
greater than 1 can be tolerated. More details can be found in the literature [2] on

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