Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 109

Now, forming the real adder,

;

x k ¼ D N 2 Db 1 ^

u k þð b 2 ^ u k 1 ^ þ b 3 ^ u k 2 Þ ð 5 : 19 Þ

^

and using an additional delay D to associate with the final adder, a real adder is
obtained:

x k ¼ D N 3 Db 1 ^ u k ^ þð b 2 ^ u k 1 ^ þ b 3 ^ u k 2 Þ ð 5 : 20 Þ

^

Finally, we choose the system delay such that D ¼ z 1 and replace u k 2 ¼ z 2 u k
and u k 1 ¼ z 1 u k , so we get

:

x k ¼ z N þ 3 z 1 b 1 ^ u k ^ þð z 1 b 2 ^ u k ^ þ z 2 b 3 ^ u k Þ ð 5 : 21 Þ

^

Removing the factor z 1

from the expression, we obtain

x k ¼ z N þ 2 f b 1 ^

þ z 1 b 3 ^ u k ^ þð b 2 ^ u k ^ u k Þg : ð 5 : 22 Þ

Note that N ¼ 2 is the minimum possible value of N for a causal filter. Choosing
N ¼ 2 gives

þ z 1 b 3 ^

x k ¼f b 1 ^

u k ^ þð b 2 ^ u k ^ u k Þg : ð 5 : 23 Þ

Equation (5.23) is very convenient for pipelining and is illustrated in Figure 5.9.
Hardware enclosed by a dotted line represents a multiplier ( ^ ) or an adder ( þ ),

taking propagation delays into account. The above procedure is general for any FIR
filter. Pipelining an FIR filter results in maximising the sampling or throughput
frequency at the expense of a delay or latency in the availability of the output. It is
like reading yesterday's paper or the day before yesterday's, every morning.

5.5.3 Pipelining IIR Filters
Pipelining an IIR filter is considerably more difficult than pipelining an FIR filter.
This is mainly because the delay in the availability of the output makes it
impossible to feed back output values with short delay, as is required for the
straightforward IIR implementation. As an example, consider a simple first-order
IIR filter

x k ¼ a 1 x k 1 þ u k : ð 5 : 24 Þ

As in the FIR case, we introduce a delay D N as follows:

x k ¼ D N ð a 1 x k 1 þ u k Þ : ð 5 : 25 Þ

^