Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 108

modelled as

b 1 ^ u k ¼ b 1 u k D 1 ¼ b 1 u k D 1 ; ð 5 : 10 Þ

where is the ideal multiplier and D 1 is the propagation delay associated with the
multiplication. The ideal adder is given as þ and the corresponding delay
associated with the adder is D 2 . Then an addition of two variables u k and u k 1
can be written as

u k

þ u k 1 ¼ð u k þ u k 1 Þ D 2 : ð 5 :

11 Þ

Each of the previous devices can be incorporated into a pipelined digital filter
structure by following it with a synchronising register. The clock period must then
be less than D þ t s þ t r , where t s is the register set-up time and t r is the register
propagation delay. With this notation we can rewrite (5.5) as

^

w k ¼ 1 : 608 w k 1 ^ 0 : 9875 w k 2 þ u k ð 5 : 12 Þ

^ ^

¼ 1 : 608 w k 1 D 1 D 1 0 : 9875 w k 2 D 1 þ D 1 u k :

ð 5 : 13 Þ

5.5.2 Pipelining FIR Filters
In this section we wish to realise

x k ¼ b 1 u k þ b 2 u k 1 þ b 3 u k 2 : ð 5 : 14 Þ

It is acceptable to have an overall delay D N but it is desirable to minimise N:

x k ¼ D N ^ f b 1 u k þ b 2 u k 1 þ b 3 u k 2 g : ð 5 : 15 Þ

First, by associating one D with each multiplier and forming real multipliers as per
the notation D ¼ , we get

^

x k ¼ D N 1 ^ f b 1 D u k þ b 2 D u k 1 þ b 3 D u k 2 g : ð 5 : 16 Þ

Now the real multiplier is formed:

x k ¼ D N 1 ^ f b 1 ^ u k þ b 2 ^ u k 1 þ b 3 ^ u k 2 g : ð 5 : 17 Þ

Next we use one additional D to associate with the adding of b 2 ^ u k 2 .

It is important to choose the most delayed values first in order to minimise N.

u k 1 and b 3 ^

x k ¼ D N 2 Db 1 ^ f u k þ D ð b 2 ^ u k 1 þ b 3 ^ u k 2 Þ g : ð 5 : 18 Þ

^