Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 92

The IE11 bit is set to 1 to enable INT11. The IFR can be read to verify that bit
IF11 is set to 1 (INT11 enabled). Writing a 1 to a bit in the interrupt set register (ISR)
causes the corresponding interrupt flag to be set in IFR, whereas a 0 to a bit in the
interrupt clear register (ICR) causes the corresponding interrupt to be cleared.
All interrupts remain pending while the CPU has a pending branch instruction.
Since a branch instruction has five delay slots, a loop smaller than six cycles is non-
interruptible. Any pending interrupt will be processed as long as there are no
pending branches to be completed. Additional information can be found in Ref. 6.
3.15 MULTICHANNEL BUFFERED SERIAL PORTS
Two McBSPs are available. They provide an interface to inexpensive (industry stan-
dard) external peripherals. McBSPs have features such as full-duplex communica-
tion, independent clocking and framing for receiving and transmitting, and direct
interface to AC97 and IIS compliant devices. They allow several data sizes between
8 and 32 bits. Clocking and framing associated with the McBSPs for input and output
are discussed in Ref. 7.
External data communication can occur while data are being moved internally.
Figure 3.4 shows an internal block diagram of a McBSP. The data transmit (DX)
and data receive (DR) pins are used for data communication. Control information
(clocking and frame synchronization) is through CLKX, CLKR, FSX, and FSR. The
CPU or DMA controller reads data from the data receive register (DRR) and writes
data to be transmitted to the data transmit register (DXR). The transmit shift reg-
ister (XSR) shifts these data to DX. The receive shift register (RSR) copies the data
received on DR to the receive buffer register (RBR). The data in RBR are then
copied to DRR to be read by the CPU or the DMA controller.
Other registers—the serial port control register (SPCR), receive/transmit control
register (RCR/XCR), receive/transmit channel enable register (RCER/XCER), pin
control register (PCR), and sample rate generator register (SRGR)—support
further data communication [7].
The two McBSPs are used for input and output through the onboard codec.
McBSP0 is used for control and McBSP1 for transmitting and receiving data.
3.16 DIRECT MEMORY ACCESS
Direct memory access (DMA) allows for the transfer of data to and from internal
memory or external devices without intervention from the CPU [7]. Sixteen
enhanced DMA channels (EDMA) can be configured independently for data trans-
fer. DMA can access on-chip memory and the EMIF, as well as the HPI. Data of
different sizes can be transferred: 8-bit bytes, 16-bit half-words, and 32-bit words.
A number of DMA registers are used to configure the DMA: address (source
and destination), index, count reload, DMA global data, and control registers. The
source and destination addresses can be from internal program memory, internal