Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 93

FIGURE 3.4. Internal block diagram of McBSP (Courtesy of Texas Instruments).
data memory, an external memory interface, and an internal peripheral bus. DMA
transfers can be triggered by interrupts from internal peripherals as well as from
external pins.
For each resource, each DMA channel can be programmed for priorities with the
CPU, with channel 0 having the highest priority. Each DMA channel can be made
to start initiating block transfer of data independently. A block can contain a number
of frames. Within each frame can be many elements. Each element is a single data
value. The DMA count reload register contains the value to specify the frame count
(16 MSBs) and the element count (16 LSBs).
3.17 MEMORY CONSIDERATIONS
3.17.1 Data Allocation
Blocks of code and data can be allocated in memory within sections specified in the
linker command file. These sections can be either initialized or uninitialized. The ini-
tialized sections are: