Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 91

TABLE 3.5 Interrupt Service Table

Interrupt Offset

RESET 000h

NMI 020h

Reserved 040h

Reserved 060h

INT4 080h

INT5 0A0h

INT6 0C0h

INT7 0E0h

INT8 100h

INT9 120h

INT10 140h

INT11 160h

INT12 180h

INT13 1A0h

INT14 1C0h

INT15 1E0h

For an interrupt to occur, the CPU must not be executing a delay slot associated
with a branch instruction.
The interrupt service table (IST) shown in Table 3.5 is used when an interrupt
begins. Within each location is an FP associated with each interrupt. The table con-
tains 16 FPs, each with eight instructions. The addresses on the right side correspond
to an offset associated with each specific interrupt. For example, the FP for inter-
rupt INT11 is at a base address plus an offset of 160 h. Since each FP contains eight
32-bit instructions (256 bits) or 32 bytes, each offset address in the table is incre-
mented by 20 h 32.

The reset FP must be at address 0. However, the FPs associated with the other
interrupts can be relocated. The relocatable address can be specified by writing this
address to the interrupt service table base (ISTB) register of the interrupt service
table pointer (ISTP) register, shown in Figure B.7. On reset, ISTB is zero. For relo-
cating the vector table, the ISTP is used; the relocatable address is ISTB plus the
offset.

=

3.14.2 Interrupt Acknowledgment

The signals IACK and INUMx (INUM0 through INUM3) are pins on the C6x that
acknowledge that an interrupt has occurred and is being processed. The four
INUMx signals indicate the number of the interrupt being processed. For example,

INUM3 = 1 (MSB), INUM2 = 0, INUM1 = 1, INUM0 = 1 (LSB)

correspond to (1011) b = 11 , indicating that INT11 is being processed.