Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 79

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0
1 0 1 1 0 1 1 0
A B C D E F G H
FIGURE 3.3. One FP with three EPs showing the “p” bit of each instruction.

3.4 FETCH AND EXECUTE PACKETS

The architecture VELOCITI, introduced by TI, is derived from the VLIW archi-
tecture. An execute packet (EP) consists of a group of instructions that can be exe-
cuted in parallel within the same cycle time. The number of EPs within a fetch packet
(FP) can vary from one (with eight parallel instructions) to eight (with no parallel
instructions). The VLIW architecture was modified to allow more than one EP to
be included within an FP.
The least significant bit of every 32-bit instruction is used to determine if the next
or subsequent instruction belongs in the same EP (if 1) or is part of the next EP (if
0). Consider an FP with three EPs: EP1, with two parallel instructions, and EP2 and
EP3, each with three parallel instructions, as follows:

Instruction A

|| Instruction B

Instruction C

|| Instruction D

|| Instruction E

Instruction F

|| Instruction G

|| Instruction H

EP1 contains the two parallel instructions A and B; EP2 contains the three par-
allel instructions C, D, and E; and EP3 contains the three parallel instructions F, G,
and H. The FP would be as shown in Figure 3.3. Bit 0 (LSB) of each 32-bit instruc-
tion contains a “p” bit that signals whether it is in parallel with a subsequent instruc-
tion. For example, the “p” bit of instruction B is zero, denoting that it is not within
the same EP as the subsequent instruction C. Similarly, instruction E is not within
the same EP as instruction F.

3.5 PIPELINING

Pipelining is a key feature in a DSp to get parallel instructions working properly,
requiring careful timing. There are three stages of pipelining: program fetch, decode,
and execute.