Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 80

1. The program fetch stage is composed of four phases:
(a) PG : program address generate (in the CPU) to fetch an address
(b) PS : program address send (to memory) to send the address
(c) PW : program address ready wait (memory read) to wait for data
(d) PR : program fetch packet receive (at the CPU) to read opcode from
memory
2. The decode stage is composed of two phases:
(a) DP : to dispatch all the instructions within an FP to the appropriate func-
tional units
(b) DC : instruction decode
3. The execute stage is composed of 6 phases (with fixed point) to 10 phases
(with floating point) due to delays (latencies) associated with the following
instructions:
(a) Multiply instruction, which consists of two phases due to one delay
(b) Load instruction, which consists of five phases due to four delays
(c) Branch instruction, which consists of six phases due to five delays

Table 3.2 shows the pipeline phases, and Table 3.3 shows the pipelining effects.
The first row in Table 3.3 represents cycle 1, 2,...,12.Each subsequent row repre-
sents an FP. The rows represented PG, PS,...illustrate the phases associated with
each FP. The program generate (PG) of the first FP starts in cycle 1, and the PG of
the second FP starts in cycle 2, and so on. Each FP takes four phases for program
fetch and two phases for decoding. However, the execution phase can take from 1

TABLE 3.2 Pipeline Phases

Program Fetch Decode Execute

PG PS PW PR DP DC E1-E6 (E1-E10 for double precision)

TABLE 3.3 Pipelining Effects

Clock Cycle

1 2 3 4 5 6 7 8 9 10 11 12

PG PS PW PR DP DC E1 E2 E3 E4 E5 E6

PG PS PW PR DP DC E1 E2 E3 E4 E5

PG PS PW PR DP DC E1 E2 E3 E4

PG PS PW PR DP DC E1 E2 E3

PG PS PW PR DP DC E1 E2

PG PS PW PR DP DC E1

PG PS PW PR DP DC