Digital Signal Processing Reference
In-Depth Information
in R
n
. Register M
n
is modifier, which defines the type of arithmetic used in the
address computation: linear, modulo, or reverse-carry. Linear addressing is used in
general-purpose addressing, modulo addressing is used with circular buffers, and
reverse-carry addressing is useful on realizing the bit-reversed permutation found
in radix-2 FFT. As there are eight register triplets, programmer can maintain eight
different type of buffers simultaneously. The EP register is stack extension pointer
and it is not used for operand addressing. Dedicated address generation units are
used in conventional DSP processors, while multi-issue processors, e.g., VLIW
processors, contain more parallel resources and arithmetic units can be used for
computing both the addresses and signals.
6
Program Control
DSP algorithms are quite often data-independent and, therefore, computations are
highly data-oriented in contrast to control-oriented algorithms containing data-
dependent computations. In addition, algorithms often define tight loops, thus DSP
processor should have efficient looping capabilities. If the loop kernel contains
only few instructions, it is clear that the loop control overhead, i.e., instructions
needed to decrement the loop counter, test against end condition, and branch, can
be significant. DSP processors often have zero-overhead looping capability (also
known as hardware looping), which means that processor has hardware support
for the decrement-test-branch sequence, thus the control overhead of software
looping can be avoided. Hardware looping, however, may introduce side effects
or constraints, e.g., interrupts are disabled during the loop execution, branches
or certain addressing modes are not allowed in loop kernels, or the number of
instructions in loop kernel is limited.
In pipelined processors, branching is an expensive operation as the destination
address of branching often is obtained in late pipeline stages implying that several
instructions have already been fetched to the pipeline but due to the branch they
should not be executed. Therefore, the pipeline needs to be flushed. This indicates
that a standard branch consumes several cycles and is called as multi-cycle branch.
One alternative method is to execute the instructions already fetched to the pipeline.
This means that instructions following immediately the branch instruction will be
executed regardless of the branch. Such a method is called as delayed branch and
the number of instructions executed after branch instructions is called as delay slot.
In decision-intensive code, branching is needed often and it would be extremely
expensive in architectures with deep pipelines. One approach to avoid multi-cycle
branching in such cases is conditional execution. This means that a condition code is
integrated to the instruction and the instruction is executed only when the condition
is true. The instruction passes through the pipeline normally and only the execution
stage is conditional.
