General-Purpose DSP Processors - Signal Processing Systems - page 781

Y ADDR BUS
X ADDR BUS
PROGRAM ADDR BUS

EP

N0 M0 R0 R4 N4 M4

N5 M5

N1 M1 R1 R5

N6
N7

M6
M7

N2
N3

M2
M3

R2
R3

R6
R7

Address ALU Address ALU

GLOBAL DATA BUS

PROGRAM ADDRESS BUS

Fig. 14 Principal block diagram of address generation unit of DSP56300

exploit delay lines, as illustrated by FIR filter example in ( 1 ) , and discrete transforms
imply block processing. In early DSP processors, delay lines were implemented as
a linear FIFO buffer in memory, which indicates that the samples need to be copied
from a memory location to the next memory location at each iteration. This implies
need for extra memory bandwidth. Similar behavior without the need for moving
data is to exploit circular buffer or ring buffer, i.e., a memory array is managed with
the aid of a pointer. Each time a new sample enters to buffer, the sample is stored to a
memory location pointed by the pointer, and then the pointer is incremented. Once
the buffer is filled and the pointer exceeds the reserved memory area, the pointer
is initialized to point to the beginning of the buffer. Pointers can be maintained in
specific address registers and updated with the aid of address ALUs. The pointer
increment behaves as a modulo arithmetic, thus circular buffers are maintained with
the aid of modulo addressing.
The previous features are used with the aid of addressing modes and the
most powerful addressing mode in DSP processors is typically register indirect
addressing with pre- or post-updates. The powerful addressing modes imply that
the a single DSP instruction specifies several operations, thus often loop kernels in
DSP processors are short compared to the corresponding kernels in general-purpose
processors.
The address generation unit of DSP56300 illustrated in Fig. 14 is an example of
an versatile and flexible address unit. Registers R n ,N n ,andM n operate as triplets
such that R n contains the address that is used to compute the effective operand
address. This register can be pre- or post-updated depending on the used selected
addressing mode. Register N n contains offset or index, which is added to the address