General-Purpose DSP Processors - Signal Processing Systems - page 780

Fig. 13 Parallel access
schemes: (a) high-order
interleaving and memory
maps with (b) high-order
interleaving, and (c)
low-order interleaving

b c

M 0
M 1
M 2
M 3
M 0

0x00
0x01
0x02
0x03
0x04

0x00
0x01
0x02
0x03
0x04
...

M 0

M 1

...

a

0x0b M 3

M 2

0x0b

r M 0

M 1

0x0c
0x0d
0x0e
0x0f

0x0c
0x0d
0x0e
0x0f

M 3

a n -1
m

... ... ... a 1 a 0

M M 3

parallel. The memory map according to low-order interleaving is shown in Fig. 13 c .
In such a case, the idea is to access various elements from the same array in parallel
rather than accessing elements from different arrays in parallel as it is often the case
in modified Harvard architecture. This is also supported by the fact that in various
processors based on Harvard architecture, the parallel memory modules reside in
different memory spaces, e.g., in DSP65300 in Fig. 11 , the parallel memory modules
are in X and Y memory spaces, thus the module is determined during programming.
Harvard architecture is not the only method to increase the memory bandwidth.
Similar performance can be obtained by exploiting multi-port memories. For
example, dual-port memory with two buses provides the same memory bandwidth
as two single port memories over to buses. The dual-port memory is, however, more
expensive in terms of area, speed, and power. On the other hand, multi-port memory
is more flexible as the same memory space is seen through the ports, thus there is
no need to distribute the data between different modules. In LSI DSP16410, three-
port memories are used such that one port is dedicated for instruction/coefficient
memory space, the second port for data memory space, and the third port is left for
DMA transfers [ 31 ] .
Multiple access memories can also be used to increase the memory bandwidth,
i.e., memory can be accessed multiple times in an instruction cycle. For example,
TMS320C54x processors contain dual-access memory [ 38 ] , which corresponds to
a Harvard architecture with two data memories. Multiple access memory is also
flexible as there is only one memory space, thus careful distribution of data is not
needed like in Harvard architecture. However, multiple access memory may restrict
the maximum clock frequency of the processor.

5 Address Generation

Intensive access to memory in DSP applications implies that address computa-
tions are performed frequently. As the data path is utilized by signal processing
arithmetic, DSP processors often contain ALUs dedicated to memory address
computations. Many of DSP applications operate over data in arrays, e.g., filters