Application-Specific Accelerators for Communications - Signal Processing Systems - page 734

Received
Sequence

Decoded
Sequence

DSP

FPGA

Fig. 5 Channel equalizer DSP/hardware accelerator partitioning

fast Fourier transform, inverse fast Fourier transform and FIR filtering as well as
despreading and descrambling.
As an example, using the workload partition criteria for partitioning functionality
between a programmable DSP core and system containing multiple hardware for a
3.5G HSDPA system, it has been shown that impressive performance results can be
obtained. In studying the bottlenecks of such systems when implemented on a pro-
grammable DSP core in software, it has been found the key bottlenecks in the system
to be the channel estimation, fast Fourier transform (FFT), inverse fast Fourier
transform (IFFT), FIR filter, and to a lesser extent despreading and descrambling
as illustrated in Fig. 4 [ 10 ] . By migrating the 3.5G implementation from a solely
software based implementation executing on a TMS320C64x based programmable
DSP core to a heterogeneous system containing not only programmable DSP cores
but also distinct hardware acceleration for the various bottlenecks, the authors
achieve almost an 11.2x speedup in the system [ 10 ] . Figure 5 illustrates the system
partitioning between programmable DSP core and hardware (e.g. FPGA or ASIC)
accelerator that resulted in load balancing the aforementioned bottlenecks.
The arrows in the diagram illustrate the data flow between local programmable
DSP core on-chip data caches and the local RAM arrays. In the case of channel
estimation, the work is performed in parallel between the programmable DSP core
and hardware acceleration. Various other portions of the workload are offloaded to
hardware based accelerators while the programmable DSP core performs the lighter
weight signal processing code and book keeping.