Digital Signal Processing Reference
In-Depth Information
Fig. 6
MIMO transmitter
and receiver
H
Tx
Rx
Despite the ability to achieve over 11x speedup in performance, it is important to
note that the experimental setup used in these studies was purposely pessimistic. The
various FFT, IFFT, etc. compute blocks in these studies were offloaded to discrete
FPGA/ASIC accelerators. As such, data had to be transferred, for example, from
local IFFT RAM cells to FIR filter RAM cells. This is pessimistic in terms of
data communication time. In most cases the number of gates required for a given
accelerator implemented in FPGA/ASIC was low enough that multiple accelerators
could be implemented within a single FPGA/ASIC drastically reducing chip-to-chip
communication time.
2.2
MIMO Detection Accelerators
systems can be used to improve the reliability and diversity in the receiver by
providing the receiver with multiple copies of the transmitted information. This
diversity gain is obtained by employing different kinds of space-time block code
N
receive antennas and over a time span of
T
time symbols, the system can be
modeled as
Y
=
HX
+
N
,
(1)
where
H
is the
N
T
space-time code
matrix where its
x
ij
element is chosen from a complex-valued constellation
×
M
channel matrix. Moreover,
X
is the
M
×
Ω
of
the order
w
and corresponds to the complex symbol transmitted from the
i
-th
antenna at the
j
-th time. The
Y
matrix is the received
N
=
|
Ω
|
T
matrix where
y
ij
is the
perturbed received element at the
i
-th receive antenna at the
j
-th time. Finally,
N
is
the additive white Gaussian noise matrix on the receive antennas at different time
slots.
MIMO systems could also be used to further expand the transmit data rate
using other space-time coding techniques, particularly layered space-time (LST)
multiplexing (SM). In the spatial multiplexing scheme, independent symbols are
transmitted from different antennas at different time slots; hence, supporting even
×
