Application-Specific Accelerators for Communications - Signal Processing Systems - page 733

Tabl e 1 Throughput performance of different MIMO systems

HSDPA+
(2

LT E
(2

LT E
(4

WiMax Rel 1.5
(2

WiMax Rel 1.5
(4 × 2MIMO) × 2MIMO) × 4MIMO) × 2MIMO) × 4MIMO)

Downlink 42 Mbps 173 Mbps 326 Mbps 144 Mbps 289 Mbps

Uplink 11.5 Mbps 58 Mbps 86 Mbps 69 Mbps 69 Mbps

Received
Bit Stream

Decoded
Bit Stream

Time

Fig. 4 Workload partition for a channel equalizer

2.1 MIMO Channel Equalization Accelerator

The total workload for a given channel equalizer performed as a baseband pro-
cessing part on the mobile receiver can be decomposed into multiple tasks as
depicted in Fig. 4 . This block diagram shows the various software processing
blocks, or kernels, that make up the channel equalizer firmware executing on the
digital signal processor of the mobile receiver. The tasks are: channel estimation
based on known pilot sequence, covariance computation (first row or column)
and circularization, FFT/IFFT (Fast Fourier transform and Inverse Fast Fourier
transform) post-processing for updating equalization coefficients, finite-impulse
response (FIR) filtering applied on the received samples (received frame), and user
detection (despreading-descrambling) for recovering the user information bits. The
computed data is shared between the various tasks in a pipeline fashion, in that the
output of covariance computation is used as the input to the matrix circularization
algorithm.
The computational complexity of various components of the workload vary with
the number of users in the system, as well as users entering and leaving the cell as
well as channel conditions. Regardless of this variance in the system conditions
at runtime, the dominant portions of the workload are the channel estimation,