Digital Signal Processing Reference
In-Depth Information
2
Hardware Accelerators for Communications
Processors in 3G and 4G cellular systems typically require high speed, throughput,
and flexibility. In addition to this, computationally intensive algorithms are used
to remove often high levels of multiuser interference especially in the presence
of multiple transmit and receive antenna MIMO systems. Time varying wireless
channel environments can also dramatically deteriorate the performance of the
transmission, further requiring powerful channel equalization, detection, and decod-
ing algorithms for different fading conditions at the mobile handset. In these types of
environments, it is often the case that the amount of available parallel computation
in a given application or kernel far exceeds the available functional units in the
target processor. Even with modern VLIW style DSPs, the number of available
functional units in a given clock cycle is limited and prevents full parallelization of
the application for maximum performance. Further, the area and power constraints
of mobile handsets make a software-only solution difficult to realize.
Figure
3
depicts a typical MIMO receiver model. Three major blocks, MIMO
channel estimator & equalizer, MIMO detector, and channel decoder, determine the
computation requirements of a MIMO receiver. Thus, it is natural to offload these
very computational intensive tasks to hardware accelerators to support high data
rate applications. Example of these applications include 3GPP LTE with 326 Mbps
downlink peak data rate and IEEE 802.16e WiMax with 144 Mbps downlink
peak data rate. Further, future standards such as LTE-Advance and WiMax-m are
targeting over 1 Gbps speeds.
Data throughput is an important metric to consider when implementing a wireless
receive. Table
1
summaries the data throughput performance for different MIMO
wireless technologies as of 2009. Given the current DSP processing capabilities,
it is very necessary to develop application-specific hardware accelerators for the
complex MIMO algorithms.
MIMO
Equalizer &
Estimator
MIMO
Encoder
MIMO
Detector
Channel
Decoder
Fig. 3
Basic structure of an MIMO receiver
