FPGA-Based DSP - Signal Processing Systems - page 722

Application
Specification

Design
Constraints

Architecture
Specification

Specification and
Requirements

Application
Implementation/
Verification

Application
Model

Mapping
Model

Architecture
Model

UML
Design

Automatic Code
Generation

Functional Simulation

UML
Interface

UML back-
annotate

UML Parsers UML Profiler

Architecture
Exploration Flow

Static Architecture
Exploration

Dynamic Architecture
Exploration

Physical Implementation

Fig. 19 Koski MPSoC design toolset

intensive applications, such as image processing operations [ 8 ] . Operations such
as motion estimation or edge detection have extreme data capacity and bandwidth
demands, necessitating detailed and convoluted design processes to derive com-
plex, multi-level memory hierarchies to make such real-time realisations feasible.
Whilst progress is being made in methodologies and automated solutions to this
problem [ 9 , 18 , 27 ] , automated creation of these multi-level hierarchies remains an
open problem.
This memory problem illustrates only one aspect of the challenges facing FPGA
DSP system designers, and vendors of tools to aid these designers—other open
issues include synthesis of multi-FPGA architectures, automated resolution of off-
chip communications, early estimation of implementation cost/performance, and
reducing the run-times of low level mapping and place and route tasks for generating
FPGA programming. Whilst these are taxing questions, the start made by the latest
generation of FPGA design tools and technologies are highly encouraging. As the
use of FPGA becomes more widespread to fill the widening gap created by the
commercial justification required for the NRE costs of fabricating custom chips,
and the power consumption and performance issues of multicore technology, the
FPGA industry must, and will, establish system design approaches and supporting
tools for its own unique needs.