Digital Signal Processing Reference
In-Depth Information
6
Summary
FPGAs offer enormous potential for implementation of custom DSP comput-
ing architectures for ad-hoc, low volume DSP systems. The suitability of their
programmable logic to host bit-parallel core architectures, and the advent of DSP-
datapath units, along with hardcore and softcore processors has given designers to
ability to harness a vast array of processing technologies with which to implement
their systems. The options range from dedicated hardware architectures, to mas-
sively parallel software programmable architectures through GPP architectures with
application specific co-processors, and everything inbetween.
Whilst this presents an enormous opportunity, it places significant stress on the
FPGA system design process. Since the entire motivation for using FPGA is it's
ability to host custom computer architectures tailored to the application, the complex
heterogeneous system synthesis process required to generate an implementation
of a DSP application is encountered frequently. As such, FPGA DSP system
design presents an architecture synthesis challenge unencountered elsewhere in the
embedded computing world. A new generation of design tools is starting to tackle
and automate solutions to this system design problem, but many advances are yet to
be made before it is solved.
References
1. Agility Design Solutions Inc.: Handel-C Language Reference Manual (2007).
URL www.
agilityds.com
2. Altera Corp.: Avalon Interface Specifications (2008). URL www.altera.com
3. Altera Corp.: Nios II C2H Compiler User Guide (2008). URL www.altera.com
4. Altera Corp.: DSP Design Flow User Guide (2009). URL www.altera.com
5. Altera Corp.: Stratix V Device Handbook (2012). URL www.altera.com
6. Banerjee, P., Haldar, M., Nayak, A., Kim, V., Saxena, V., Parkes, S., Bagchi, D., Pal, S.,
Tripathi, N., Zaretsky, D., Anderson, R., Uribe, J.: Overview of a compiler for synthesizing
MATLAB programs onto FPGAs. IEEE Trans. VLSI Syst. 12 (3), 312-324 (2004)
7. Cho, J., Chang, H., Sung, W.: An FPGA-based simd processor with a vector memory unit. In:
Proc. IEEE International Symposium on Circuits and Systems, pp. 525-528 (2006)
8. Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., Zhang, Z.: High-level synthesis
for FPGAs: From prototyping to deployment. IEEE Trans, on Computer-Aided Design of
Integrated Circuits and Systems 30 (4), 473-491 (2011)
9. Fischaber, S., Woods, R., McAllister, J.: SoC memory hierarchy derivation from dataflow
graphs. Journal of Signal Processing Systems (2009)
10. Gajski, D., Vahid, F., Narayan, S., Gong, J.: Specification and Design of Embedded Systems.
Prentice Hall (1994)
11. Gajski, D.D., Abdi, S., Gerstlauer, A., Schirner, G.: Embedded System Design: Modeling,
Synthesis and Verification. Springer, New York (2009)
12. Harriss, T., Walke, R., Kienhuis, B., Deprettere, E.F.: Compilation from matlab to process
networks realised in FPGA. Design Automation for Embedded Systems 7 (4), 85-403 (2002)
13. Hoare, C.: Communicating Sequential Processes. Prentice Hall (1985)
14. Inc., S.: PICO FPGA Datasheet (2009). URL www.synfora.com
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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