FPGA-Based DSP - Signal Processing Systems - page 721

5.2 Compaan/LAURA

The Compaan toolchain is composed of the Compaan parallelising compiler and the
LAURA architectural synthesis tool. It has predominately targetted core network
implementations of Static Affine Nested Loop Programs (SANLPs) written in
Matlab on FPGA [ 34 ] . Compaan acts as a parallelising compiler for the sequential
specification, once again generating a KPN application specification. The LAURA
tool then assumes either a fixed allocation of a one-to-one correspondence between
the KPN structure and the target architecture [ 34 ] . Design space exploration of the
implementation is affected by manipulating the KPN topology using transforma-
tions of the loops (e.g. skewing, unrolling) in the source SANLP [ 12 , 33 ] .

5.3 Koski

Koski is a Unified Modelling Language (UML)-based design environment for
automatic programming, synthesis and exploration of MPSoC implementations
of wireless sensor network applications [ 17 ] . The structure of the Koski design
environment is outlined in Fig. 19 . The final architecture is composed of multi-
ple processors and cores connected to a HIBI network [ 29 ] . Again, application
specification uses the KPN modelling domain. This specification, along with a
specification of the architecture and of the implementation constraints, is processed
by an architecture exploration toolset to generate the platform allocation. During
static mapping, the allocation of processors, and mapping of tasks to processors is
generated, with this allocation fine-tuned during a dynamic mapping phase. Upon
finalisation of the mapping, the RTL and software synthesis technology of Koski is
used to generate a prototype of the final implementation.

5.4 Open Issues in the Design of FPGA DSP Systems

The key to productive DSP system design on FPGA is the ability to quickly generate
a wide range of implementations from which the designer can choose a suitable
candidate. Given the range of techniques which may be used to implement DSP
systems, as outlined in this chapter, highly promising technologies to fulfill this
requirement are in evidence, but substantial problems remain.
Specifically, the heterogeneity of the resources on modern FPGA are significantly
complicating the FPGA design process. For instance, whilst C-based synthesis
tools such as AutoESL are capable of producing FPGA architectures to per-
form the computational requirements of a DSP application, they are much less
well-developed in terms of synthesising complex memory structures for memory