FPGA-Based DSP - Signal Processing Systems - page 720

Application
(C/C++)

System Level Architecture Exploration
(Sesame)

Parallelisation
(KPNGen)

High Level
Models

Platform Spec.
(XML)

Mapping Spec.
(XML)

Kahn Process
Network (XML)

IP Library

RTL Models

System Level Synthesis (ESPAM)

Platform
Netlist

IP Cores
(VHDL)

Processor
C/C++

Auxiliary
Files

RTL Synthesis
(Commerical Tools - Xilinx Platform Studio … )

Device
Netlist

Fig. 18 Daedalus MPSoC design flow

existing tools, Sesame [ 26 ] andESPAM [ 24 ] , Daedalus enables a full synthesis flow
from sequential application specification to implementation in a variety of MPSoC
topologies, including point-to-point, bus-based or crossbar interconnect. The flow
of data and operations in Daedalus is illustrated in Fig. 18 .
The upper processes are mostly aimed at generating an allocation of processing
resources, with the lower processes aimed at synthesis of the allocation. The
functional specification of the system to be implemented, written as a Static Affine
Nested Loop Program (SANLP) in a standard sequential language such as C++ or
Matlab, is converted to a parallel Kahn Process Network form [ 16 ] bythe KPNGen
tool [ 38 ] . Daedalus accepts this specification and performs an exhaustive search of
the design space to produce an MPSoC allocation which can support the real-time
requirements of the system. The platform specification and mapping of the KPN
tasks to distinct processors in the platform are then generated and passed to ESPAM
for synthesis of the solution.