FPGA-Based DSP - Signal Processing Systems - page 719

To maintain a productive design process in this environment it is vital that a
designer can quickly evaluate a range of options for implementing their architecture,
and choose the one which best matches their needs, applying some fine-tuning
afterwards if required. This should all occur, preferably, without the designer having
to resort to low abstraction, i.e. RTL level, manipulation of the architecture. To
enable this kind of process a new generation of system design tools which allow
rapid generation of FPGA architectures is beginning to emerge which help explore
the trade-offs of resource, power, and real-time performance. A number of these are
described in Sect. 5 .

5 System Level Design for FPGA DSP

FPGA architecture development has historically been sustained by the use of RTL
HDL-based coding, and implementation techniques similar to those employed for
ASIC development [ 11 ] . However, as the complexity of ASICs increases along
with the cost of fabricating a chip, the design and use of ASIC is increasingly
confined to mass-market technologies such as mobile phones and PCs, all of which
employ popular communications standards such as Bluetooth ® , WiFi, and codecs
such as MPEG. This has driven development of standards-based programmable SoC
platforms which are highly efficient at implementing a set of standards in a particular
area, for example 802.11 wireless communications protocols, or a variety of MPEG
codecs, and programmable to realise specific standards from the target set [ 19 , 39 ] .
Consequently, the majority of SoC design tools are intended for a design process
which may take a substantial period of time to build a highly efficient architecture
once. This is distinct from FPGA-based design where architecture re-engineering
is commonplace. A divergence in the nature of design tools supporting ASIC and
FPGA design is a natural consequence.
Multiprocessor architectures, on the other hand, do not require any architectural
manipulation, merely reprogramming. As such the requirement to frequently and
rapidly generate custom computing architectures encountered in FPGA is unique.
To maintain design productivity in this process, tools which enable this design
process must quickly and automatically generate an architecture from an abstract
representation of the algorithm functionality, and should be able to automatically
explore the design space trading off performance with power and resource before
automatically generating the implementation. A number of tools which enable this
process for FPGA-based systems are beginning to emerge.

5.1 Daedalus

Daedalus is a system level design and rapid implementation toolset for DSP
applications which has been used to generate FPGA-based MPSoC implementations
of various image processing algorithms [ 23 , 36 ] . A conglomerate of two previously