FPGA-Based DSP - Signal Processing Systems - page 705

ranging from small, high bandwidth DisRAM-like units for data storage close
to the datapath, to the low-bandwidth, bulk off-chip storage mechanisms. The
general structures of these hierarchies in Virtex ® and Stratix ® FPGA are outlined in
Sects. 3.3.1 and 3.3.2 .

Virtex ® Memory Hierarchy 3.3.1

In addition to the DisRAM configuration option of the Virtex ® LFG outlined in
Sect. 3.1.1 , the latest generation of Xilinx FPGA have a three-tier memory hierarchy
similar to that found in conventional microprocessor, except that in FPGA the
absolute storage size and bandwidth at each level of the hierarchy is controlled by
the designer, within physical capacity limits. On the chip, the DisRAM resource
offered by the programmable logic is augmented by a series of dedicated, hardwired
BRAM components on the chip [ 46 ] .
In Virtex ® FPGA these take the form of a number of 36 Kb RAMs, each of
can be configured to implement a dual-port 36 Kb BRAM, or two dual-port 18 Kb
BRAMs. Configuration of the memory may take either form without resorting
to use of the programmable routing resource of the FPGA device; further, two
BRAMs may be cascaded to implement a 64 Kb BRAM without accessing the
FPGA routing resource. Virtex ® -7 devices support between 795 and 1,880 of these
BRAM components.
In addition, since the streaming nature of signal processing applications means
that First-In-First-Out (FIFO) queues offer a simple, highly effective data buffering
scheme, Virtex ® BRAMs may be configured for use in this mode. They have extra
logic integrated, including counters, comparators and status flag generation logic
for this purpose. Each BRAM can implement one FIFO. The architecture of such a
FIFO, which does not require programmable fabric resource, is shown in Fig. 9 .

Stratix ® Memory Hierarchy

3.3.2

The Stratix ® FPGA family has a different approach to memory, employing a
dedicated two-level hierarchy, composed of 640 bit Memory Logic Array Blocks
(MLABs) and 20 Kbit M20K blocks. The structure of each level, and their intended
uses are outlined in Table 3 .
The MLAB resource is highly flexible, enabling customised balancing of
capacity and bandwidth, with each offering storage of 64 8, 9 or 10 bit words, or
32 16, 18 or 20 bit words. The M20K is similarly flexible, trading off capacity and
wordwidth between 512—16 K storage of 40 bit—1 bit words. Furthermore, each
resource can operate in a number of modes:

￿ Single Port : 1 word read or written per cycle

￿ Simple Dual Port : Dual port behaviour, with one read and one write operation

per cycle.