FPGA-Based DSP - Signal Processing Systems - page 704

Stratix ® -V FPGA DSP block constitution
Multipliers

Tabl e 2

18 × 18 18 × 18

16 × 16 27 × 27 Multiply- Multiply+

Device DSPB 9 × 9 18 × 18 36 × 18 Add 36 bit Add

5GSD3 600 1,800 1,200 600 1,200 600

5GSD4 1,044 3,132 2,088 1,044 2,088 1,044

5GSD5 1,590 4,770 3,180 1,590 3,180 1,590

5GSD6 1,775 5,325 3,550 1,775 3,550 1,775

5GSD8 1,963 5,889 3,926 1,963 3,926 1,963

Each DSP block can operate in one of five basic modes, based around various
configurations of the MAC function fundamental to DSP operations, the five classes
being [ 5 ] :

1. Independent Multiplier : Parallel multiplication configurations, varying from
three 9 18 multiplier.

2. Independent Complex Multiplier : Exploits compositions of multiple DSPBs to
achieve complex multiplication.
3. Multiplier Adder Sum : Cascaded compositions of DSPBs to achieve multiply-
add-sum operation.
4. Sum Of Square : One DSP block can support a single sum-of-squares computa-
tion.
5. 18

× 9 multipliers, two 16 × 16 or one 27 × 27, 18 × 18 or 36 ×

× 18 Multiplicand + 36 bit Summand : One full resolution 18 × 18 multiply-

add operation can be achieved in a single DSPB.
6. Systolic FIR : Cascaded DSPBs can achieve FIR filter operation for fully
dynamic inputs, one dynamic input and one coefficient input, or one coefficient
and one pre-adder output.
In addition, the Stratix ® -V DSP block has dedicated rounding and saturation
logic after the second stage adder, and the pipelining level of the device is
configurable.

3.3 FPGA Memory Hierarchy in DSP System Implementation

Real-time implementation of DSP applications requires careful architecture design
such that the datapath components, which perform the mathematical calculations,
offer high enough computational capacity, and that these have sufficient input and
output data bandwidth to keep them fed with data and continuously operating. This
situation becomes particularly significant when implementing image processing
applications on FPGA, where storage of entire frames of image data on-chip is
sometimes not feasible [ 9 ] , whilst storage in off-chip memory incurs significant
data bandwidth and synchronisation problems. To help alleviate this issue, recent
generations of FPGA device have exhibited a distinct hierarchy of memory storage,