FPGA-Based DSP - Signal Processing Systems - page 706

waddr raddr

wrcount

wrcount

BRAM

din/dinp do/dop

wrclk
wren
rst

rdclk
rden Status Flag Logic

Virtex ®

Fig. 9 BRAM-based FIFO architecture [ 46 ]

Stratix ® -V memory hierarchy
Stratix V E Resource

Tabl e 3

Resource Bits/Block 5SEE9 5SEEB Use

MLAB 640 15,850 2,640 FIFO buffers, filter delay lines

M20K 9,216 17,960 2,640 General purpose

￿ True Dual Port : Dual port behaviour with full read-write capability for each

port per cycle—only support by M20K.

￿ Shift Register : Support for variable width, length and number of taps for filtering

and correlation functions.

￿ ROM : Both MLAB and M20K can implement an intialisable ROM operation.

￿ FIFO : MLABs are ideal for small shallow FIFOs, with M20K enabling longer

queues.

4 FPGA Design Processes

As outlined in Sect. 2 , modern FPGA provide a diverse range of logic, compu-
tational and memory components for creation of custom DSP architectures. It is
clear that strong similarities are evident across these devices in the form of distinct
programmable logic, DSP-datapath and memory hierarchy resources in both Xilinx