Integrated Modeling Using Finite State Machines and Dataflow Graphs - Signal Processing Systems - page 985

SysteMoC

Forte Cynthesizer

SystemC

behavioral synthesis

model

select CPUs, busses

hw accelerators,
etc. from the component

library component library

specify mapping

exploration

includes

model

CPUs, busses,

hardware accelerators etc.

design space
exploration

optimized

select
implementation

rapid
prototyping

solutions

Fig. 20 Design flow using S YSTEM C O D ESIGNER : The application is given by a S YSTE M O Cbe-
havioral model. Forte Cynthesizer [ 16 ] is used to automatically synthesize hardware accelerators.
Design space exploration using multi-objective evolutionary algorithms automatically searches
for the best architecture candidates. The entire hardware/software implementation is prototyped
automatically for FPGA-based platforms. The S YSTE M O C behavioral model of the application is
used for both automatic design space exploration and creation of hardware accelerators allowing
for rapid prototyping

sis, (iii) determination of their performance parameters like required hardware
resources, throughput and latency or estimated software execution times, (iv)
design space exploration for finding the best candidate architectures, and (v)
rapid prototype generation for FPGA platforms. The design flow implemented by
S YSTEM C O D ESIGNER is shown in Fig. 20 .
ThefirststepintheS YSTEM C O D ESIGNER design flow is to describe the
application in form of a S YSTE M O C model. Each S YSTE M O C actor can then be
transformed and synthesized into both hardware accelerators and software modules.
Whereas the latter one is achieved by simple code transformations, the hardware
accelerators are built by high level synthesis using Forte Cynthesizer [ 16 ] . This
allows for quick extraction of important performance parameters like the achieved
throughput and the required area by a particular hardware accelerator. In case of
Xilinx FPGAs used as target platform, hardware resources in form of flip flops,
look-up tables, and block RAMs are estimated. These values can be used to evaluate
different solutions found during automatic design space exploration.
The performance information together with the executable specification and a so-
called architecture template serve as the input model for design space exploration
(cf. Fig. 20 ) . The architecture template is represented by a graph which contains all
possible hardware accelerators, processors, memories, and the communication in-
frastructure from which the design space exploration has to select those ones which
are necessary in order to fulfill the user requirements in terms of overall throughput