Integrated Modeling Using Finite State Machines and Dataflow Graphs - Signal Processing Systems - page 984

description file into a header instantiating all actors and FIFOs and their initial token
valuation, (2) translating the CAL actor itself by emitting all the actions and internal
state variables as C code by an intermediate step via the C Intermediate Language
[ 31 ] and its pretty printer, and (3) by emitting code corresponding to the action
schedule responsible for the activation of the actions in the functionality. This code
corresponds to the guards, the schedule FSM , and the priority specification of the
CAL actor.
The hardware synthesis tool CAL2HDL [ 25 ] starts by evaluating the NL dataflow
description deriving the set of actors to synthesize and their parameters. Each actor
in this set is synthesized separately, i.e., no scheduling strategy optimization is
applied, resulting in purely self-scheduled actor system. The actor synthesis pro-
ceeds from the XML intermediate representation by inserting the actor parameters
from the NL dataflow description as constants into the actors performing constant
propagation and inlining all functions into actions. The resulting intermediate
representation is self-contained, i.e., it is no longer referencing any external
functions. After this, the intermediate representation is transformed to SSA form.
The next step is the generation of a corresponding hardware module for each
action by translating the SSA representation to RTL via behavioral compilation, i.e.,
generating multiplex/demultiplex logic for register access, generating control logic
for control flow elements (if-then-else, looping constructs,

), and static scheduling
of operators where possible. Furthermore, a central scheduler hardware module is
instantiated, responsible for executing the schedule FSM by evaluating the guards
and selecting a highest priority transition to execute from the priority specification
of the CAL actor. All these modules communicate via usage of RTL signals. Finally,
network synthesis is performed by a straightforward transformation of the dataflow
graph from the NL dataflow description into a corresponding hardware structure.
Edges in the dataflow graph are translated to FIFOs with the sizes specified in the NL
file. Furthermore, actors instantiations in NL may have clock domain annotations.
Therefore, actors in the same clock domain are connected via usage of synchronous
FIFOs while actors in different domains are connected via asynchronous FIFOs.

...

4.3 SystemCoDesigner

S YSTEM C O D ESIGNER [ 27 ] is a hardware/software codesign framework supporting
the synthesis of implementations from S YSTE M O C [ 13 ] models. It provides timing
simulation for possible architecture mappings as well as software and hardware
synthesis backends for S YSTE M O C.

4.3.1 Overview

The overall design flow of the S YSTEM C O D ESIGNER design methodology is
basedon(i)abehavioralS YSTE M O C model of an application, (ii) generation
of hardware accelerators from S YSTE M O C modules using behavioral synthe-