Digital Signal Processing Reference
In-Depth Information
and chip size. The fewer components are allocated, the fewer hardware resources
are required. This, however, in general comes along with a reduction in throughput,
thus leading to tradeoffs between execution speed and implementation costs. Multi-
to find sets of optimized solutions.
From this set of optimized solutions, the designer selects a hardware/software
implementation best suited for his needs. Once this decision has been made, the last
step of the proposed ESL design flow is the rapid prototyping of the corresponding
FPGA-based implementation. The implementation is assembled by interconnecting
the hardware accelerators and processors of the selected implementation with
special communication modules provided in a component library. Furthermore,
the program code for all microprocessors is generated by compiling source code
derived from the S
YSTE
M
O
C model and linking it with a run-time library for the
microprocessor. Finally, the entire platform is compiled into an FPGA bit stream
5
Exploiting Static MoCs For Scheduling
In this section, novel methods for exploiting static MoCs embedded in more general
dataflow graphs will be presented. In this context, clustering methods for the
purpose of multi-processor scheduling are of particular interest.
5.1
SysteMoC Clustering
Generating
program code
from a dataflow graph for microprocessor target requires
a scheduling strategy for the actors mapped to this microprocessor. While
static
dataflow graphs. However, real world designs also contain dynamic actors. The most
basic strategy used is to postpone all scheduling decisions to run-time (
dynamic
scheduling
) with the resulting significant scheduling overhead and, hence, a reduced
system performance. However, this strategy is suboptimal if it is known that
some of the actors exhibit regular communication behavior like
SDF
and
CSDF
actors. The scheduling overhead problem could be mended by coding the actors
of the application at an appropriate level of granularity, i.e., combining as much
functionality into one actor that the computation costs dominate the scheduling
overhead. This can be thought of as the designer manually making clustering
decisions. However, the appropriate level of granularity is chosen by the designer
by trading schedule efficiency improving bandwidth against resource consumption
(e.g., buffer capacities), and scheduling flexibility improving latency. Aggregation
of functionality into one actor can also mean that more data has to be produced and
consumed atomically which requires larger buffer capacities and may delay data
