Hardware Reference
In-Depth Information
selector instead of an address. This selector designates a descriptor called a
call
gate
, which gives the address of the procedure to be called. Thus it is not possible
to branch into the middle of an arbitrary code segment at a different level. Only
official entry points may be used.
A possible use for this mechanism is suggested in Fig. 6-16. At level 0, we
find the kernel of the operating system, which handles I/O, memory management,
and other critical matters. At level 1, the system call handler is present. User pro-
grams may call procedures here to have system calls carried out, but only a specific
and protected list of procedures may be called. Level 2 contains library proce-
dures, possibly shared among many running programs. User programs may call
these procedures but may not modify them. Finally, user programs run at level 3,
which has the least protection. Like the Core i7's memory-management scheme,
the protection system is closely based on MULTICS.
Traps and interrupts use a mechanism similar to the call gates. They, too, ref-
erence descriptors, rather than absolute addresses, and these descriptors point to
specific procedures to be executed. The
TYPE
field in Figure 6-13 distinguishes
between code segments, data segments, and the various kinds of gates.
The OMAP4430 ARM CPU is a 32-bit machine and supports a paged virtual
memory based on 32-bit virtual addresses that are translated to a 32-bit physical
address space. As such, an ARM CPU can support up to 2
32
bytes (4 GB) of physi-
cal memory. Four page sizes are supported: 4 KB, 64 KB, 1 MB, and 16 MB. The
mappings implied by these four page sizes are illustrated in Fig. 6-17.
Bits
20
12
16
16
12
20
10
22
Virtual
Address
4K virtual
page no.
64K virtual
page no.
1M virtual
page no.
16M virtual
page no.
Offset
Offset
Offset
Offset
Physical
Address
4K page
frame
64K page
frame
1M page
frame
16M page
frame
Offset
Offset
Offset
Offset
Bits
20
12
16
16
12
20
10
22
Figure 6-17.
Virtual-to-physical mappings on the OMAP4430 ARM CPU.
The OMAP4430 ARM CPU uses a page-table structure similar to that of the
Core i7. The page-table mapping for a 4-KB virtual address page is shown in
Fig. 6-18(a). The first-level descriptor table is indexed with the most significant 12
bits of the virtual address. The first-level descriptor-table entry indicates the physi-
cal address of the second-level descriptor table. This address, combined with the
next 8 bits of the virtual address, produce the page-descriptor address. The page
descriptor contains the address of the physical page frame plus permission infor-
mation regarding page accesses.
