Hardware Reference
In-Depth Information
In both cases, the destination is always a register. Sufficient encoding space is pro-
vided for up to 16 instructions, all of which are currently used.
With 32-bit instructions, it is not possible to include a 32-bit constant in the in-
struction. The
MOVT
instruction sets the 16 upper bits of a 32-bit register, leaving
room for another instruction to set the remaining lower 16 bits. It is the only in-
struction to use this format.
Every 32-bit instruction has the same 4-bit field in the most significant bits
(bits 28 to 31). This is the condition field, which makes any instruction a
predi-
cated instruction
. A predicated instruction executes as normal in the processor,
but before writing its result to a register (or memory), it first checks the condition
of the instruction. For ARM instructions, the condition is based on the state of the
processor status register (
PSR
). This register holds the arithmetic properties of the
last arithmetic operation, (e.g., zero, negative, overflowed, etc). If the condition is
not met, the result of the conditional instruction is dropped.
The branch instruction format encodes the largest immediate value, used to
compute a target address for branches and function procedure calls. This instruc-
tion is special, because it is the only one where 24 bits of data are needed to speci-
fy an address. For this instruction, there is a single, 3-bit opcode. The address is
the target address divided by four, making the range approximately
2
25
bytes rela-
±
tive to the current instruction.
Clearly, the ARM ISA designers wanted to fully utilize every bit combination,
including otherwise illegal operand combinations, for specifying instructions. The
approach makes for extremely complicated decoding logic, but at the same time, it
allows the maximum number of operations to be encoded into a fixed-length 16- or
32-bit instruction.
The ATmega168 has six simple instruction formats, as illustrated in Fig. 5-15.
Instructions are 2 or 4 bytes in length. Format one consists of an opcode and two
register operands, both of which are inputs and one is also the output of the instruc-
tion. The
ADD
instruction for registers uses this format, for example.
Format 2 is also 16 bits, consisting of an additional 16 opcodes and a 5-bit reg-
ister number. This format increases the number of operations encoded in the ISA
at the cost of reducing the number of instruction operands to one. Instructions that
use this format perform a unary operation, taking a single register input and writing
the output of the operation to the same register. Examples of this type of instruc-
tion include ''negate'' and ''increment.''
Format 3 has an 8-bit unsigned immediate operand. To accommodate such a
large immediate value in a 16-bit instruction, instructions which use this encoding
can have only one register operand (used as an input and output) and the register
can only be
R16
-
R31
(which limits the operand encoding to 4 bits). Also, the
