THE INSTRUCTION SET ARCHITECTURE LEVEL - Structured Computer Organization - page 371

Format

15 0

1 00cc ccrd dddd rrrr ALU: Opcode(c) Rd, Rr

2 1001 010d dddd cccc Extended ALU: Opcode(c) Rd

3 01cc KKKK dddd KKKK ALU + Imm: Opcode(c) Rd, #K

4 10Q0 QQcd dddd cQQQ Load/store: Id/st(c) X/Y/Z+Q, Rd

5 11cc KKKK KKKK KKKK Branch: br(c) PC + K

31 0

6 1001 010K KKKK 11cK KKKK KKKK KKKK KKKK

Call/jmp: call/jmp(c) #K

Figure 5-15. The ATmega168 AVR instruction formats.

number of opcode bits is cut in half, allowing only four instructions to use this for-
mat ( SUBCI , SUBI , ORI , and ANDI ).
Format 4 encodes load and store instruction, which includes a 6-bit unsigned
immediate operand. The base register is a fixed register not specified in the instruc-
tion encoding because it is implied by the load/store opcode.
Formats 5 and 6 are used for jumps and procedure calls. The first format in-
cludes a 12-bit signed immediate value that is added to the instruction's PC value
to compute the target of the instruction. The last format expands the offset to 22
bits, by making the AVR instruction 32 bits in size.

5.4 ADDRESSING

Most instructions have operands, so some way is needed to specify where they
are. This subject, which we will now discuss, is called addressing .

5.4.1 Addressing Modes

Up until now, we have paid little attention to how the bits of an address field
are interpreted to find the operand. It is now time to investigate this subject, called
address modes . As we shall see, there are many ways to do it.