Hardware Reference
In-Depth Information
operands and a single destination register. The 16-bit instructions are pared-down
versions of the 32-bit instruction. They perform the same operations, but allow
only two register operands (i.e., the destination register must be the same as one of
the inputs) and only the first eight registers can be specified as inputs. The ARM
architects called this smaller version of the ARM ISA the Thumb ISA.
Additional variants allows instructions to supply a 3, 8, 12, 16, or 24-bit un-
signed constant instead of one of the registers. For a load instruction, two registers
(or one register and an 8-bit signed constant) are added together to specify the
memory address to read. The data are written into the other register specified.
The format of the 32-bit ARM instructions is illustrated in Fig. 5-14. The
careful reader will notice that some of the formats have the same fields (e.g.,
LONG MULTIPLY and SWAP ). In the case of the SWAP instruction, the decoder
knows that the instruction is a SWAP only when it sees that the combination of field
values for the MUL is illegal. Additional formats have been added for instruction
extensions and the Thumb ISA. At the time of this writing, the number of instruc-
tion formats was 21 and rising. (Can it be long before we see some company
advertising the ''World's most complex RISC machine''?) The majority of instruc-
tions, however, still use the formats shown in the figure.
Instruction type
31
2827
1615
87
0
Cond
00
I Opcode
S
S
Rn
Rd
Operand2
Data processing / PSR Transfer
Cond
0 0 0 0 0 0
A
Rd
RdHi
Rn
RS
1001
1001
1001
Rm
Multiply
Long Multiply
Swap
Load/Store Byte/Word
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
00001
00010
01
100
000
000
101
U
A
S
RdLo
RS
Rm
B
BW
W
W
W
00
Rn
Rd
Rd
0000
Rm
I
P
U
U
U
U
L
L
L
L
Rn
Offset
Register List
P
S
Rn
Load/Store Multiple
Halfword transfer: Immediate offset
Halfword transfer: Register offset
Branch
P
1
Rn
Rd
Rd
Offset1
1
S
S
H
H
1
Offset2
P
0
Rn
0000
1
1
Rm
L
Offset
0001 0010 1111 1111 1111 0001
Rn
Branch Exchange
Coprocessor data transfer
Coprocessor data operation
Coprocessor register transfer
110
P
U
N
W
L
Rn
CRd
CPNum
Offset
1110
1110
1111
Op1
CRn
CRd
CPNum
Op2 0
1 CRm
CRm
Op1
LCRn
Rd
SWI Number
CPNum
Op2
Software interrupt
Figure 5-14. The 32-bit ARM instruction formats.
Bits 26 and 27 of every instruction are the first stop in determining the instruc-
tion format and tell hardware where to find the rest of the opcode, if there is more.
For example, if bits 26 and 27 are both zero, and bit 25 is zero (operand is not an
immediate), and the input operand shift is not illegal (which indicates the instruc-
tion is a multiply or branch exchange), then both sources are registers. If bit 25 is
one, then one source is a register and the other is a constant in the range 0 to 4095.
Search WWH ::




Custom Search