THE MICROARCHITECTURE LEVEL - Structured Computer Organization - page 287

dead cycles are not common, but they do occur, so merging Main1 into the end of
each microinstruction sequence is worth doing. All it costs is a little control store.
Thus we have our first technique for reducing path length:
Merge the interpreter loop into the end of each microcode sequence.

A Three-Bus Architecture

What else can we do to reduce execution path length? Another easy fix is to
have two full input buses to the ALU, an A bus andaBbus,giving three buses in
all. All (or at least most) of the registers should have access to both input buses.
The advantage of having two input buses is that it then becomes possible to add
any register to any other register in one cycle. To see the value of this feature, con-
sider the Mic-1 implementation of ILOAD , shown again in Fig. 4-25.

Label Operations Comments

iload1 H = LV MBR contains index; copy LV to H

iload2 MAR = MBRU + H; rd MAR = address of local variable to push

iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write

iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack

iload5 TOS = MDR; goto Main1 Update TOS

Main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch

Figure 4-25. Mic-1 code for executing ILOAD .

We see here that in iload1 LV is copied into H . The reason is so it can be added
to MBRU in iload2 . In our original two-bus design, there is no way to add two arbi-
trary registers, so one of them first has to be copied to H . With our new three-bus
design, we can save a cycle, as shown in Fig. 4-26. We have added the interpreter
loop to ILOAD here, but doing so neither increases nor decreases the execution path
length. Still, the additional bus has reduced the total execution time of ILOAD from
six cycles to five cycles. Now we have our second technique for reducing path
length:
Go from a two-bus design to a three-bus design.

Label Operations Comments

iload1 MAR = MBRU + LV; rd MAR = address of local variable to push

iload2 MAR = SP = SP + 1 SP points to new top of stack; prepare write

iload3 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack

iload4 TOS = MDR Update TOS

iload5 PC = PC + 1; fetch; goto (MBR) MBR already holds opcode; fetch index byte

Figure 4-26. Three-bus code for executing ILOAD .