THE MICROARCHITECTURE LEVEL - Structured Computer Organization - page 286

This concept of overlapping the beginning of the instruction can be carried fur-
ther, and in fact, the main-loop can in some cases be reduced to nothing. This can
occur in the following way. Consider each sequence of microinstructions that ter-
minates by branching to Main1 . At each of these places, the main loop microin-
struction can be tacked on to the end of the sequence (rather than at the beginning
of the following sequence), with the multiway branch now replicated many places
(but always with the same set of targets). In some cases the Main1 microinstruc-
tion can be merged with previous microinstructions, since those instructions are
not always fully utilized.
In Fig. 4-23, the dynamic sequence of instructions is shown for a POP instruc-
tion. The main loop occurs before and after every instruction; in the figure we
show only the occurrence after the POP instruction. Notice that the execution of
this instruction takes four clock cycles: three for the specific microinstructions for
POP and one for the main loop.

Label Operations Comments

pop1 MAR = SP = SP − 1; rd Read in next-to-top word on stack

pop2 Wait for new TOS to be read from memory

pop3 TOS = MDR; goto Main1 Copy new word to TOS

Main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch

Figure 4-23. Original microprogram sequence for executing POP .

In Fig. 4-24 the sequence has been reduced to three instructions by merging
the main-loop instructions, taking advantage of a clock cycle when the ALU is not
used in pop2 to save a cycle and again in Main1 . Be sure to note that the end of
this sequence branches directly to the specific code for the subsequent instruction,
so only three cycles are required total. This little trick reduces the execution time
of the next microinstruction by one cycle, so, for example, a subsequent IADD goes
from four cycles to three. It is thus equivalent to speeding up the clock from 250
MHz (4-nsec microinstructions) to 333 MHz (3-nsec microinstructions) for free.

Label Operations Comments

pop1 MAR = SP = SP − 1; rd Read in next-to-top word on stack

Main1.pop PC = PC + 1; fetch MBR holds opcode; fetch next byte

pop3 TOS = MDR; goto (MBR) Copy new word to TOS; dispatch on opcode

Figure 4-24. Enhanced microprogram sequence for executing POP.

The POP instruction is particularly well suited for this treatment, because it has
a dead cycle in the middle that does not use the ALU. The main loop, however,
does use the ALU. Thus to reduce the instruction length by one within an instruc-
tion requires finding a cycle in the instruction where the ALU is not in use. Such