THE MICROARCHITECTURE LEVEL - Structured Computer Organization - page 275

executed, the IJVM opcode to execute is already present in MBR . What the micro-
instruction does is branch to the microcode for executing this IJVM instruction and
also begin fetching the byte following the opcode, which may be either an operand
byte or the next opcode.
Now we can reveal the real reason each microinstruction explicitly names its
successor, instead of having them executed sequentially. All the control store ad-
dresses corresponding to opcodes must be reserved for the first word of the corres-
ponding instruction interpreter. Thus from Fig. 4-11 we see that the code that
interprets POP starts at 0x57 and the code that interprets DUP starts at 0x59. (How
does MAL know to put POP at 0x57? Possibly there is a file that tells it.)
Unfortunately, the code for POP is three microinstructions long, so if placed in
consecutive words, it would interfere with the start of DUP . Since all the control
store addresses corresponding to opcodes are effectively reserved, the micro-
instructions other than the initial one in each sequence must be stuffed away in the
holes between reserved addresses. For this reason, there is a great deal of jumping
around, so having an explicit microbranch (a microinstruction that branches) every
few microinstructions to hop from hole to hole would be very wasteful.
To see how the interpreter works, let us assume, for example, that MBR con-
tains the value 0x60, that is, the opcode for IADD (see Fig. 4-11). In the one-

microinstruction main loop we accomplish three things:
1. Increment the PC, leaving it containing the address of the first byte
after the opcode.
2. Initiate a fetch of the next byte into MBR . This byte will always be
needed sooner or later, either as an operand for the current IJVM in-
struction or as the next opcode (as in the case of the IADD instruction,
which has no operand bytes).
3. Perform a multiway branch to the address contained in MBR at the
start of Main1 . This address is equal to the numerical value of the op-
code currently being executed. It was placed there by the previous
microinstruction. Note carefully that the value being fetched in this
microinstruction does not play any role in the multiway branch.
The fetch of the next byte is started here so it will be available by the start of the
third microinstruction. It may or may not be needed then, but it will be needed
eventually, so starting the fetch now cannot do any harm in any case.
If the byte in MBR happens to be all zeros, the opcode for a NOP instruction,
the next microinstruction is the one labeled nop1 , fetched from location 0. Since
this instruction does nothing, it simply branches back to the beginning of the main
loop, where the sequence is repeated, but with a new opcode having been fetched
into MBR .
Once again we emphasize that the microinstructions in Fig. 4-17 are not con-
secutive in memory and that Main1 is not at control store address 0 (because nop1