Hardware Reference
In-Depth Information
must be at address 0). It is up to the microassembler to place each microinstruc-
tion at a suitable address and link them together in short sequences using the
NEXT ADDRESS
field. Each sequence starts at the address corresponding to the
numerical value of the IJVM opcode it interprets (e.g.,
POP
starts at 0x57), but the
rest of the sequence can be anywhere in the control store, and not necessarily at
consecutive addresses.
Now consider the IJVM
IADD
instruction. The microinstruction branched to by
the main loop is the one labeled
iadd1
. This instruction starts the work specific to
IADD
:
1.
TOS
is already present, but the next-to-top word of the stack must be
fetched from memory.
2.
TOS
must be added to the next-to-top word fetched from memory.
3. The result, which is to be pushed on the stack, must be stored back
into memory, as well as stored in the
TOS
register.
In order to fetch the operand from memory, it is necessary to decrement the
stack pointer and write it into
MAR
. Note that, conveniently, this address is also the
address that will be used for the subsequent write. Furthermore, since this location
will be the new top of stack,
SP
should be assigned this value. Therefore, a single
operation can determine the new value of
SP
and
MAR
, decrement
SP
, and write it
into both registers.
These things are accomplished in the first cycle,
iadd1
, and the read operation
is initiated. In addition,
MPC
gets the value from
iadd1
's
NEXT ADDRESS
field,
which is the address of
iadd2
, wherever it may be. Then
iadd2
is read from the
control store. During the second cycle, while waiting for the operand to be read in
from memory, we copy the top word of the stack from
TOS
into
H
, where it will be
available for the addition when the read completes.
At the beginning of the third cycle,
iadd3
,
MDR
contains the addend fetched
from memory. In this cycle it is added to the contents of
H
, and the result is stored
back to
MDR
, as well as back into
TOS
. A write operation is also initiated, storing
the new top-of-stack word back into memory. In this cycle the
goto
has the effect
of assigning the address of
Main1
to
MPC
, returning us to the starting point for the
execution of the next instruction.
If the subsequent IJVM opcode, now contained in
MBR
, is 0x64 (
ISUB
), almost
exactly the same sequence of events occurs again. After
Main1
is executed, control
is transferred to the microinstruction at 0x64 (
isub1
). This microinstruction is fol-
lowed by
isub2
and
isub3
, and then
Main1
again. The only difference between this
sequence and the previous one is that in
isub3
, the contents of
H
are subtracted
from
MDR
rather than added to it.
The interpretation of
IAND
is almost identical to that of
IADD
and
ISUB
, except
that the two top words of the stack are bitwise ANDed together instead of being
added or subtracted. Something similar happens for
IOR
.
