Hardware Reference
In-Depth Information
Label Operations Comments
ireturn1 MAR = SP = LV; rd Reset SP, MAR to get link pointer
ireturn2 Wait for read
ireturn3 LV = MAR = MDR; rd Set LV to link ptr; get old PC
ireturn4 MAR = LV + 1 Set MAR to read old LV
ireturn5 PC = MDR; rd; fetch Restore PC; fetch next opcode
ireturn6 MAR = SP Set MAR to write TOS
ireturn7 LV = MDR Restore LV
ireturn8 MDR = TOS; wr; goto Main1 Save return value on original top of stack
Fig. 4-17.
The microprogram for the Mic-1 (part 3 of 3).
given for each microinstruction: the symbolic label, the actual microcode, and a
comment. Note that consecutive microinstructions are not necessarily located in
consecutive addresses in the control store, as we have already pointed out.
By now the choice of names for most of the registers in Fig. 4-1 should be ob-
vious:
CPP
,
LV
, and
SP
are used to hold the pointers to the constant pool, local vari-
ables, and the top of the stack, respectively, while
PC
holds the address of the next
byte to be fetched from the instruction stream.
MBR
is a 1-byte register that se-
quentially holds the bytes of the instruction stream as they come in from memory
to be interpreted.
TOS
and
OPC
are extra registers. Their use is described below.
At certain times, each of these registers is guaranteed to hold a certain value,
but each can be used as a temporary register if needed. At the beginning and end
of each instruction,
TOS
contains the value of the memory location pointed to by
SP
, the top word on the stack. This value is redundant since it can always be read
from memory, but having it in a register often saves a memory reference. For a
few instructions maintaining
TOS
means
more
memory operations. For example,
the
POP
instruction throws away the top word and therefore must fetch the new
top-of-stack word from the memory into
TOS
.
The
OPC
register is a temporary (i.e., scratch) register. It has no preassigned
use. It is used, for example, to save the address of the opcode for a branch instruc-
tion while
PC
is incremented to access parameters. It is also used as a temporary
register in the IJVM conditional branch instructions.
Like all interpreters, the microprogram of Fig. 4-17 has a main loop that
fetches, decodes, and executes instructions from the program being interpreted, in
this case, IJVM instructions. Its main loop begins on the line labeled
Main1
.It
starts with the invariant that
PC
has previously been loaded with an address of a
memory location containing an opcode. Furthermore, that opcode has already
been fetched into
MBR
. Note this implies, however, that when we get back to this
location, we must ensure that
PC
has been updated to point to the next opcode to be
interpreted and the opcode byte itself has already been fetched into
MBR
.
This initial instruction sequence is executed at the beginning of every instruc-
tion, so it is important that it be as short as possible. Through careful design of the
Mic-1 hardware and software, we have reduced the main loop to only a single
microinstruction. Once the machine has started, every time this microinstruction is
