Hardware Reference
In-Depth Information
using an explicit bus line that indicates that an I/O device is being referenced, and
not memory. If we use the other approach,
memory-mapped I/O
, then we must
assign it 4 bytes of the memory space for the three ports and the control register.
The choice is somewhat arbitrary. We will choose memory-mapped I/O because it
illustrates some interesting issues in I/O interfacing.
The EPROM needs 2 KB of address space, the RAM also needs 2K of address
space, and the PIO needs 4 bytes. Because our example address space is 64K, we
must make a choice about where to put the three devices. One possible choice is
shown in Fig. 3-60. The EPROM occupies addresses to 2K, the RAM occupies ad-
dresses 32 KB to 34 KB, and the PIO occupies the highest 4 bytes of the address
space, 65532 to 65535. From the programmer's point of view, it makes no dif-
ference which addresses are used; however, for interfacing it does matter. If we
had chosen to address the PIO via the I/O space, it would not need any memory ad-
dresses (but it would need four I/O space addresses).
EPROM at address 0
RAM at address 8000H
PIO at FFFCH
0
4K 8K 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K 60K 64K
Figure 3-60.
Location of the EPROM, RAM, and PIO in our 64-KB address space.
With the address assignments of Fig. 3-60, the EPROM should be selected by
any 16-bit memory address of the form 00000xxxxxxxxxxx (binary). In other
words, any address whose 5 high-order bits are all 0s falls in the bottom 2 KB of
memory, hence in the EPROM. Thus, the EPROM's chip select could be wired to
a 5-bit comparator, one of whose inputs was permanently wired to 00000.
A better way to achieve the same effect is to use a five-input
OR
gate, with the
five inputs attached to address line
s
A
11
to
A15
. If and only if all five lines are 0
will the output be 0, thus asserting
CS
(which is asserted low). This addressing ap-
proach is illustrated in Fig. 3-60(a) and is called full-address decoding.
The same principle can be used for the RAM. However, the RAM should re-
spond to binary addresses of the form 10000xxxxxxxxxxx, so an additional
inverter is needed as shown in the figure. The PIO address decoding is somewhat
more complicated, because it is selected by the
fo
ur addresses of the form
11111111111111xx. A possible circuit that asserts
CS
only when the correct ad-
dress appears on the address bus is shown in the figure. It uses two eight-input
NAND
gates to feed an
OR
gate.
However, if the computer really consists of only the CPU, two memory chips,
and the PIO, we can use a trick to greatly simplify the address decoding. The trick
