Hardware Reference
In-Depth Information
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512K × 8
Memory
chip
4096K × 1
Memory
chip
D
(4 Mbit)
(4 Mbit)
RAS
CAS
CS
WE
OE
CS
WE
OE
(a)
(b)
Figure 3-30.
Two ways of organizing a 4-Mbit memory chip.
being written rather than being read. Finally, the
OE
(Output Enable) signal is
asserted to drive the output signals. When it is not asserted, the chip output is
disconnected from the circuit.
In Fig. 3-30(b), a different addressing scheme is used. Internally, this chip is
organized as a 2048
2048 matrix of 1-bit cells, which gives 4 Mbits. To address
the chip,
first
a row is selected by putting its 11-bit number on the address pins.
Then the
RAS
(Row Addre
ss S
trobe) is asserted. After that, a column number is
put on the address pins and
CAS
(Column Address Strobe) is asserted. The chip re-
sponds by accepting or outputting one data bit.
Large memory chips are often constructed as
n
×
n
matrices that are addressed
by row and column. This organization reduces the number of pins required but
also makes addressing the chip slower, since two addressing cycles are needed, one
for the row and one for the column. To win back some of the speed lost by this de-
sign, some memory chips can be given a row address followed by a sequence of
column addresses to access consecutive bits in a row.
Years ago, the largest memory chips were often organized like Fig. 3-30(b).
As memory words have grown from 8 bits to 32 bits and beyond, 1-bit-wide chips
began to be inconvenient. To build a memory with a 32-bit word from 4096K
×
1
chips requires 32 chips in parallel. These 32 chips have a total capacity of at least
16 MB, whereas using 512K
×
8 chips requires only four chips in parallel and al-
lows memories as small as 2 MB. To avoid having 32 chips for memory, most chip
manufacturers now have chip families with 4-, 8-, and 16-bit widths. And the
situation with 64-bit words is even worse, of course.
×
