Hardware Reference
In-Depth Information
V
CC
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
F
F
ABC
ABC
(a)
(b)
Figure 3-12.
(a) An eight-input multiplexer. (b) The same multiplexer wired to
compute the majority function.
parallel-to-serial data converter. By putting 8 bits of data on the input lines and
then stepping the control lines sequentially from 000 to 111 (binary), the 8 bits are
put onto the output line in series. A typical use for parallel-to-serial conversion is
in a keyboard, where each keystroke implicitly defines a 7- or 8-bit number that
must be output over a serial link, such as USB.
The inverse of a multiplexer is a
demultiplexer
, which routes its single input
signal to one of 2
n
outputs, depending on the values of the
n
control lines. If the
binary value on the control lines is
k
, output
k
is selected.
Decoders
As a second example, we will now look at a circuit that takes an
n
-bit number
as input and uses it to select (i.e., set to 1) exactly one of the 2
n
output lines. Such
a circuit, illustrated for
n
3 in Fig. 3-13, is called a
decoder
.
To see where a decoder might be useful, imagine a small memory consisting of
eight chips, each containing 256 MB. Chip 0 has addresses 0 to 256 MB, chip 1
has addresses 256 MB to 512 MB, and so on. When an address is presented to the
memory, the high-order 3 bits are used to select one of the eight chips. Using the
circuit of Fig. 3-13, these 3 bits are the three inputs,
A
,
B
, and
C
. Depending on
the inputs, exactly one of the eight output lines,
D
0
,...,
D
7
, is 1; the rest are 0.
Each output line enables one of the eight memory chips. Because only one output
line is set to 1, only one chip is enabled.
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