Digital Signal Processing Reference
In-Depth Information
3.1 CPLDs and FPGAs
Internally, CPLDs and FPGAs typically contain multiple copies of a basic
programmable logic element (LE) or cell. The logic element can implement a
network of several logic gates that then feed into 1 or 2 flip-flops. Logic
elements are arranged in a column or matrix on the chip. To perform more
complex operations, logic elements can be automatically connected to other
logic elements on the chip using a programmable interconnection network. The
interconnection network is also contained in the CPLD or FPGA. The
interconnection network used to connect the logic elements contains row and/or
column chip-wide interconnects. In addition, the interconnection network often
contains shorter and faster programmable interconnects limited only to
neighboring logic elements.
When a design approaches the device size limits, it is possible to run out of
either gate, interconnect, or pin resources when using a CPLD or FPGA.
CPLDs tend to have faster and more predictable timing properties while FPGAs
offer the highest gate densities and more features.
Clock signals in large FPGAs normally use special low-skew global clock
buffer lines. These are dedicated pins connected to an internal high-speed bus.
This special bus is used to distribute the clock signal to all flip-flops in the
device at the same time to minimize clock skew. If the global clock buffer line
is not used, the clock is routed through the chip just like a normal signal. The
clock signal could arrive at flip-flops at widely different times since
interconnect delays will vary in different parts of the chip. This delay time can
violate flip-flop setup and hold times and can cause metastability or
unpredictable operation in flip-flops. Most large designs with a common clock
that is used throughout the FPGA will require the use of the global clock buffer.
Figure 3.4
Examples of FPGAs and advanced high pin count package types.
The size of CPLDs and FPGAs is typically described in terms of useable or
equivalent gates. This refers to the maximum number of two input NAND gates
available in the device. This should be viewed as a rough estimate of size only.
