Digital Signal Processing Reference
In-Depth Information
The internal architecture of three examples of CPLD and FPGA device
technologies, the Altera MAX 7000, the Altera Cyclone, and the Xilinx 4000
family will now be examined. An example of each of these devices is shown in
Figure 3.4. From left to right the chips are an Altera MAX 7128S CPLD in a
Plastic J-Lead Chip Carrier (PLCC), an Altera Cyclone 10K70 FPGA in a
Plastic Quad Flat Pack (PQFP), and a Xilinx XC4052 FPGA in a ceramic Pin
Grid Array Package (PGA). The PGA package has pins on .1" centers while the
PQFP has pins on .05" centers at the edges of the package. Both Altera and
Xilinx devices are available in a variety of packages.
Packaging can represent a significant portion of the FPGA chip cost. The
number of I/O pins on the FPGA package often limits designs. Larger ceramic
packages such as a PGA with more pins are more expensive than plastic.
3.2 Altera MAX 7000S Architecture - A Product Term CPLD
Device
The multiple array matrix (MAX) 7000S is a CPLD device family with 600 to
20,000 gates. This device is configured by programming an internal electrically
erasable programmable read only memory (EEPROM). Since an EEPROM is
used for programming, the configuration is retained when power is removed.
This device also allows in-circuit reprogrammability.
LAB Local Array
This respresents a
multiplexer
controlled by the
configuration
program
Parallel Logic
Expanders
(from other
macrocells)
Global
Clear
Global
Clock
Programmable
Register
To I/O
Control
Block
PRN
Product
Term
Select
Matrix
Q
D
Clock/
Enable
Select
ENA
CLRN
Clear
Select
VCC
To PIA
Shared Logic
Expanders
16 Expander
Product
36 Signals
from PIA
Figure 3.5
MAX 7000 macrocell.
The 7000 device family contains from 32 to 256 macrocells of the type seen in
Figure 3.5. Similar to the early PALs, an individual macrocell contains five
programmable AND gates with wide inputs that feed into an OR gate with a
programmable inversion at the output. Just like a PAL, the AND/OR network is
