Digital Signal Processing Reference
In-Depth Information
Small PLDs can replace several older fixed function TTL-style parts in a
design. Most PLDs contain a PLA-like structure in which a series of AND gates
with selectable or programmable inputs, feed into an OR gate. In PALs, the OR
gate has a fixed number of inputs and is not programmable. The AND gates and
OR gate are programmed to directly implement a sum-of-products Boolean
equation. On many PLDs, the output of the OR gate is connected to a flip-flop
whose output can then be feed back as an input into the AND gate array. This
provides PLDs with the capability to implement simple state machines. A PLD
can contain several of these AND/OR networks.
Figure 3.3
Using a PLA to implement a Sum of Products equation.
In more recent times, higher densities, higher speed, and cost advantages have
enabled the use of programmable logic devices in a wider variety of designs.
CPLDs and FPGAs are the highest density and most advanced programmable
logic devices. Designs using a CPLD or FPGA typically require several weeks
of engineering effort instead of months. These devices are also sometimes
collectively called field programmable logic devices (FPLDs).
ASICs and full custom designs provide faster clock times than CPLDs or
FPGAs since they are hardwired and do not have programmable interconnect
delays. Since ASICs and full custom designs do not require programmable
interconnect circuitry they use less chip area, less power, and have a lower per
unit manufacturing cost in large volumes. Initial engineering and setup costs for
ASICs and full custom designs are much higher.
For all but the most time critical design applications, CPLDs and FPGAs have
adequate speed with maximum clock rates typically in the range of 50-
400MHz; however, clock rates up to 1GHz have been achieved on new
generation FPGAs and many have a few high-speed 1-10 GHz output pins.
