Digital Signal Processing Reference
In-Depth Information
Product Term:
Two or more factors in a Boolean expression combined with an AND
operator constitute a product term, where "product" means "logic product."
Programmable switch:
A user programmable switch that can connect a logic element
or input/output element to an interconnect wire or one interconnect wire to another.
Project:
A project consists of all files that are associated with a particular design,
including all subdesign files and ancillary files created by the user or by Quartus II
software. The project name is the same as the name of the top-level design file without
an extension.
Propagation delay:
The time required for any signal transition to travel between pins
and/or nodes in a device.
Radix:
A number base. Group logic level and numerical values are entered and
displayed in binary, decimal, hexadecimal, or octal radix in Quartus II.
Reset:
An active-high input signal that asynchronously resets the output of a register
to a logic Low (0) or a state machine to its initial state, regardless of other inputs.
Range:
A subset of the possible values of a scalar type.
Register:
A memory device that contains several latches or flip-flops that are clocked
from the same clock signal.
Resource:
A resource is a portion of a device that performs a specific, user-defined
task (e.g., pins, logic cells, interconnection network).
Retargetting:
A process of translating a design from one FPGA or other technology
to another. Retargetting involves technology-mapping optimization.
Reset:
An active-high input signal that asynchronously resets the output of a register
to a logic Low (0) or a state machine to its initial state, regardless of other inputs.
Ripple Clock:
A clocking scheme in which the Q output of one flip-flop drives the
Clock input to another flip-flop. Ripple clocks can cause timing problems in complex
designs.
RTL:
Acronym for Register Transfer Level. The model of circuit described in VHDL
that infers memory devices to store results of processing or data transfers. Sometimes
it is referred to as a dataflow-style model.
Scalar:
A data type that has a distinct order of its values, allowing two objects or
literals of that type to be compared using relational operators.
Semicustom:
General category of integrated circuits that can be configured directly
by the user of an IC. It includes gate arrays and FPGA devices.
Signal:
In VHDL a data object that has a current value and scheduled future values at
simulation times. In RTL models signals denote direct hardware connections.
Simulation:
Process of modeling a logical design and its stimuli in which the
simulator calculates output signal values.
Slew rate:
Time rate of change of voltage. Some FPGAs permit a fast or slow slew
rate to be programmed for an output pin.
Slice:
A one-dimensional, contiguous array created as a result of constraining a larger
one-dimensional array.
SOPC:
Acronym for System On-a Programmable Chip. SOPC systems contain a hard
or soft core processor in the FPGA in addition to other user logic.
Speed performance:
The maximum speed of a circuit implemented in an FPGA. It is
set by the longest delay through any for combinational circuits, and by maximum
clock frequency at which the circuit operates properly for sequential circuits.
